H. Peter Anvin
· Msg 1342 · kommentar
2018-01-29 18:25
Ärende: Fröjdepinnar
Precis. Upptäckte att Vin < 0 V och > Vdd är faktiskt officiellt
specifierat i databladen till 74HC-serien så länge strömmen är externt
begränsad till typ ±20 mA så de funkar som både buffer och
pulsgenerator: SCK ligger normalt hög, men när RTS ändrar polaritet --
oavsett riktning -- så pulsar den SCK låg i 1,5-2 µs. Det gör att bara
en OUT behövs per bit. Idén kanske känns igen från b.la. minnesvärlden
under namnet DDR :)
;;
;; Read a byte from the serial port in SPI mode
;; Bit order is MSB first (standard for SPI)
;; Data loaded into A; BC and DE clobbered
;; After 8 bits, the clock phase is the same as initial
;;
;; Total time including setup/return is 320 cycles, averaging
;; 75.0 kbps. Peak rate (sender need to keep up) is 88.2 kbps.
;;
;; The cassette port is not modified, as long as it is not
;; changed from an interrupt while this routine is running.
;;
spi_get_byte:
in a,(58) ; 10
and 0F7h ; 7 - Output zero byte; don't confuse
sender
ld d,a ; 4
xor 10h ; 7 - Opposite clock phase
out (58),a ; 11 - Generate first clock pulse
ld e,a ; 4
ld c,58 ; 7
in a,(58) ; 10 - bit 7
out (c),d ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 6
out (c),e ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 5
out (c),d ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 4
out (c),e ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 3
out (c),d ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 2
out (c),e ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 1
out (c),d ; 12
rra ; 4
rl b ; 8
in a,(58) ; 10 - bit 0
rra ; 4
ld a,b ; 4
rla ; 4
ret ; 10
;;
;; Send a byte to the serial port in SPI mode
;; Bit order is MSB first (standard for SPI)
;; Call with data in A; AF, BC and DE clobbered
;; After 8 bits, the clock phase is the same as initial
;;
;; Total time including setup/return is 307 cycles, averaging
;; 78.2 kbps. Peak rate (target need to keep up) is 111.1 kbps
;; (for the last bit only; other bits are 96.8 kbps)
;;
;; The cassette port is not modified, as long as it is not
;; changed from an interrupt while this routine is running.
;;
spi_send_byte:
; Rotate the data byte into proper position for OUT
; (MSB/bit 7 -> bit 3)
rlca ; 4
rlca ; 4
rlca ; 4
rlca ; 4
ld b,a ; 4
ld c,08h ; 7 - Mask for data bit
in a,(58) ; 10
and 0F7h ; 8 - Initial port state without data bit
ld d,a ; 4 - Initial phase
xor 10h ; 8
ld e,a ; 4 - Opposite phase
ld a,b ; 4
and a,c ; 4
or e ; 4
out (58),a ; 11 - bit 7
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or d ; 4
out (58),a ; 11 - bit 6
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or e ; 4
out (58),a ; 11 - bit 5
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or d ; 4
out (58),a ; 11 - bit 4
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or e ; 4
out (58),a ; 11 - bit 3
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or d ; 4
out (58),a ; 11 - bit 2
ld a,b ; 4
rlca ; 4
ld b,a ; 4
and a,c ; 4
or e ; 4
out (58),a ; 11 - bit 1
ld a,b ; 4
rlca ; 4
and a,c ; 4
or d ; 4
out (58),a ; 11 - bit 0
ret ; 10
